1. Field of the Invention
The present invention relates to a semiconductor device having an MOS transistor (Metal-Oxide-Semiconductor Field Effect Transistor: MOSFET), and more particularly to a dynamic random access memory (DRAM) having memory cells comprising MOSFET and a capacitor.
2. Description of the Related Art
MOSFET is widely used as a basic element constituting a semiconductor integrated circuit. Particularly in a DRAM which enables large capacity memory, MOSFET plays a very important role as a transistor for switching used for a memory cell.
The storage principle of a DRAM is storing charge in a capacitor and controlling the in and out of the charge by a MOSFET for switching. A memory cell 101 for one bit is comprised of a cell transistor 102 (transistor for switching) and a capacitor 103, as shown in FIG. 17. For interconnects, a word line 104 and a bit line 105 are placed. The word line 104 is connected to a gate of the cell transistor 102, and the bit line 105 is connected to one of source-drain regions of the cell transistor 102. The other of the source-drain regions of the cell transistor 102 is connected to the capacitor 103. Although FIG. 17 shows only one memory cell, in an actual DRAM, many such memory cells are placed in a two dimensional matrix.
As mentioned above, in the two source-drain regions of the cell transistor 102, the bit line 105 and a capacitor 103 are connected respectively. The potentials of the bit line 105 and the capacitor 103 are not fixed, and one becomes a higher or lower potential than the other frequently according to the operation state of the DRAM. In an n-channel MOSFET, for example, an n+ region at the high potential side, out of the two n+ regions formed on both sides of a gate, functions as a drain, and an n+ region at the low potential side functions as a source. However in a cell transistor, it is not fixed which n+ region becomes a higher potential (or lower potential), so both regions are called “source-drain regions”. For a p-channel MOSFET as well, the two p+ regions are both called “source-drain regions”.
To record one bit, voltage is applied to the word line 104 first, to turn the cell transistor 102 ON, and the charge is supplied from the bit line 105 to the capacitor 103 (or the charge stored in the capacitor 103 is discharged to the bit line 105).
When charging to (or discharging from) the capacitor 103 completes, the cell transistor 102 is turned OFF, so that the charge stored in the capacitor 103 is not discharged even if the potential of the bit line 105 drops (or the empty capacitor 103 is not charged even if the potential of the bit line 105 rises). In this way, one bit of information is stored in the memory cell 101.
However the-charge stored in the capacitor 103 is gradually discharged over time, so the same storage content must be rewritten before the memory is deleted. This rewriting operation is called “refresh”.
As shown in FIG. 18, the above mentioned discharge is generated by the current 106 which leaks from the source-drain region at the capacitor 103 side to the back gate 107. This leak current will be described in more detail. FIG. 19 is an example of the cross-sectional view of memory cells. FIG. 19 shows two memory cells 101. The capacitor 103 is a trench type capacitor. In the two cell transistors 102, respective source-drain regions are combined and form one region 109. The bit line 105 is connected to this region. By this structure, the area for connecting the bit line 105 and the source-drain regions of the memory cells are decreased to half, and the degree of integration of the DRAM improves.
In the example shown in FIG. 19, the cell transistor 102 is an n-channel MOSFET. Therefore the source-drain regions 108 and 109 are n+ regions. The back gate region 107 is a p type Si. On the p type semiconductor layer positioned between the source-drain regions 108 and 109, the word line 104, which functions as a gate, runs in a vertical direction with respect to the page face via a thin gate oxide film. The word line 104 functions as a gate of the cell transistor 102 which is a MOSFET. These memory cells are electrically isolated from other memory cells by an element isolation layer 130, which is thick SiO2 film. The memory cells are also electrically isolated from the substrate by a pnp structure comprised of a p-type back gate region 107, n-type internal potential layer 131, and p type substrate 132 (“n+” is written as “N+” in FIG. 19).
In a DRAM, 0V or less potential is applied to the back gate region 107. The potential of the source-drain regions 108 and 109 changes in the 0V or higher range. Therefore to the pn junction comprised of the source-drain regions 108 and 109 and the back gate region 107, back bias is always being applied. Because of this, very little current 106 leaks from the source-drain region 108 to the back gate region 107. However, since the capacity of the capacitor 103 is small, the capacitor 103 is gradually discharged even by this very small leak current. The current 106 which leaks into the back gate region 107 enters the back gate power supply, and eventually reaches the ground.
This discharging phenomena is called a “junction leak”, and is a major cause of the capacitor 103 being discharged. In a DRAM, in order to replenish the discharged charge, charge 116 is frequently re-injected to the capacitor 103 from the bit line 105, as shown in FIG. 20. This operation is called “refresh”. Refresh is repeated in a short cycle (e.g. 100 ms), as shown in FIG. 21, and is repeated before the potential of the capacitor 103 drops to the minimum potential 110, recognized as high level (Non-Patent Document “Semiconductor Engineering, Second Edition”, Tokyo Denki University 2004, p. 187).
If the leak current 106 from the capacitor 103 is excessive, the capacitor 103 cannot be recharged sufficiently even if the charge is re-injected from the bit line 105. Given this situation, the memory cell 101 does not function as a storage element.
To prevent such a situation, the junction leak is suppressed by optimizing the fabrication steps in prior art, so as to maintain good memory holding characteristics.